A semiconductor integrated circuit may have a high voltage control device to which a high voltage is directly applied in order to directly control an external system that uses a high voltage. Such a high voltage control device may be needed in a circuit that requires a high breakdown voltage.
A CMOS device with small power consumption may generally be widely used as a high voltage control device. The CMOS device may include a PMOS (P-type MOS) transistor and an NMOS(N-type MOS) transistor. Each transistor may have a double diffused drain structure having the same conductive type lightly-doped region as a source and a drain formed at a lower part of the source and drain regions to obtain a high breakdown voltage.
In an MOSFET device having such a double diffused drain structure, a high voltage may be applied to a gate electrode and a drain region. Thereupon, a high electric field may be formed between the gate electrode and a substrate or between the drain region and the substrate. Meaning, as a high electric field is formed in a region adjacent to the drain region and the gate electrode, a problem that the breakdown voltage decreases arises.
Accordingly, a MOSFET device having an offset-LOCOS (Local Oxidation of Silicon) structure has been proposed in order to prevent decrease in breakdown voltage that arises in a MOSFET device having a double diffused drain structure.
Example FIG. 1 illustrates a cross sectional view of a MOSFET having a LOCOS structure and may include Referring to FIG. 1 an MOSFET device having an offset-LOCOS structure according to the conventional art includes n+ source/drain regions 141 spaced apart from each other in a predetermined region in P−type semiconductor substrate 100. Source/drain region 141 is disposed in an n− extended drain region acting as a drift region, for example, n− drift region 103. Also formed in a surface of substrate 100 between n+ source/drain region 141 and n− drift region 103 is channel forming region 101. Gate electrodes, i.e., gate insulating film pattern 121 and gate conductive film pattern 122 are sequentially disposed on and/or over channel forming region 101. N+ source/drain regions 141 are electrically connected to source electrode S and drain electrode D. As a device isolation film of such an MOSFET device, LOCOS device isolation film 111 is used.
LOCOS device isolation film 111 plays a role of increasing the thickness of both sides of gate insulating film pattern 121. By this, a high electric field applied to both sides of gate insulating film pattern 121 is distributed to both sides of gate insulating film pattern 121 at the time of device isolation, thus relieving stress caused by the electric field in these regions. As the thickness of gate insulating film pattern 121 increases, the electric stress caused by the electric field decreases.
Characteristics of the above MOSFET formed by a LOCOS process are determined by the thickness A of LOCOS device isolation film 111, the size B of a channel operating at a high voltage, the size C of channel forming region 101 operating in a low voltage region, and the size D from the starting point of n−drift region 103 to the bird's beak S of LOCOS device isolation film 111. To adjust the sizes B, C, and D, the size and thickness A of LOCOS device isolation film 111 function as the largest variable, however, there is a problem that it is generally difficult to adjust the size and thickness A of device isolation film 111 formed by the LOCOS method. In other words, since it is difficult to control the bird's beak S portion of device isolation film 111 by the process condition, it is impossible to adjust the thickness A of device isolation film 111. Therefore, there is a problem that the characteristics of the MOSFET become worse because the sizes B, C, and D are arbitrarily changed due to the size of the bird's beak S. That is, if the size D becomes larger due to the bird's beak S, a single channel can be formed in conjunction with C, and if the size D becomes smaller, a well breakdown voltage may be a problem. Additionally, because n− drift region 103 is formed within semiconductor substrate 100 below device isolation film 111, the size and doping concentration of n− drift region 103 become irregular due to the unevenness of the thickness A of device isolation film 111, thereby deteriorating the characteristics of the MOSFET.